The present invention pertains generally to variable impedance output drivers in integrated circuits, and more particularly to a novel hybrid code for controlling the output impedance of integrated circuit output drivers due to variations in manufacturing process, voltage, and temperature.
Integrated circuits are commonly packaged as chips. An integrated circuit communicates with devices outside the chip via input and output signal pads on the exterior of the chip. Inside the chip, the signal pads are connected to signal receiver and signal driver circuitry, as appropriate, to receive incoming signals or to drive outgoing signals.
The signal pads on a chip are connected to the packaging of the chip (e.g., a pin) which is then typically connected to respective signal traces on a printed circuit board. The signal traces may connect the chip to other integrated circuit chips, electronic devices, or connectors on the printed circuit board that connect to external (i.e., off-board) devices. The electrical connection between the signal pad of the integrated circuit die and signal trace of the printed circuit board through the packaging of the chip is characterized by parasitic resistance, inductance, and capacitance, which interferes with the transmission of the signal from the signal pad. The transmission line characteristics of the printed circuit board signal trace itself, including parasitic resistance, capacitance, and inductance, also interfere with the quality of the transmission of the signal from the signal pad. All of the foregoing add to the load impedance which must be driven by the output driver circuit.
Due to the parasitic resistance, capacitance, and inductance which is present on chip-to-chip signal transmission lines, the driver circuits that drive those transmission lines typically includes circuitry designed to avoid excessive voltage swings, or “ringing”, when signal switching occurs. Ringing must be avoided while still switching as fast as possible to meet the high speed performance requirements of modern integrated circuits.
As known by those skilled in the art, it is important to match the output impedance of a given signal driver to the characteristic impedance of the transmission line it drives in order to avoid signal reflections due to voltage level switching on the pad, and therefore undesirable signal degradation.
Matching the impedance of an output driver to the characteristic impedance of the signal transmission line is problematic for several reasons. First, process variations inherent in the manufacturing process of integrated circuits, such as the transistor implanting doping level, the effective length of channels in the field effect transistors (FETs), the thickness of the gate oxide for transistors, and the diffusion resistance, can cause the output impedance of two supposedly identical circuits to differ. In particular, variations in any or all of the above process parameters can cause different integrated circuits intended to perform the same function to be classified as “slow”, “nominal”, or “fast”. In other words, two supposedly identical integrated circuits can vary in any or all of the process parameters. As these parameters approach the fast case, the resistance of many components within a chip is decreased. In the opposite extreme, as the process parameters stray further and further from the ideal case, the performance of the chip is degraded, specifically, the resistance of the many components within the chip is increased. This situation is referred to as the “slow” case.
In addition, variations in voltage and temperature can cause variations in the output impedance of a given chip. Specifically, the driver output impedance can vary significantly between variations in the operating voltage even within a small operating voltage tolerance range. In another example, when the temperature of an integrated circuit approaches its maximum operating temperature, the resistance of the integrated circuit components increases.
In view of the above, variable impedance output drivers have been developed to allow adjustment of the driver output impedance due to variations in manufacturing process, voltage, and temperature. Typically the characteristic impedance of transmission lines connected to I/O pads of the output drivers are known and/or can be measured, and once known or measured, a precision external resistor REXT of corresponding value may be provided on the printed circuit board to serve as a reference impedance from which to match. Alternatively, instead of precision external resistor REXT, other types of arrangements can be used.
It is becoming standard to use a programmable impedance network to match the impedance of an output signal pad driven by an output driver to the external resistor REXT. In an impedance network, a plurality of impedance legs, each of which is characterized by a predetermined impedance, are programmably connectable between a voltage source and a node coupled to an output pad driven by an output driver. As known in the art, the term “node” refers to a pad, a trace, a wire, an electrical conductor, or any electrically connected combination and/or equivalent thereof, such that any point of the “node” is characterized by the same electrical state as all other points of the “node”, subject to a margin of error determined by the characteristic resistance, capacitance, and inductance between points of the node. When an appropriate combination of parallel legs of the impedance network are actively connected between the voltage source and node, such that a voltage VDIV measured at a reference point is one half (½) a voltage V applied across the series combination of the external resistor REXT and the active parallel legs of the impedance network, then it is known that the external resistor REXT and active parallel legs of transistors within the impedance network are equally sharing/dividing the voltage V. That is, if two series portions are equally sharing/dividing a voltage, then such two series portions have the same impedance. Accordingly, as a result of the above method, the output impedance of the pad coupled to the output driver is “adapted” to external resistor REXT, as the active parallel legs of the impedance network are providing an impedance (e.g., resistance) which matches that of external resistor REXT.
The above “adaptive” procedure may be performed not only upon initialization (e.g., reset) of the integrated circuit, but may also be continuously or periodically performed during operation of the integrated circuit. Such continuous/periodic operation is advantageous because environmental parameters (e.g., voltage, temperature, etc.) of the integrated circuit change over time (e.g., the integrated circuit becomes hotter with operation which changes on-die impedances), and thus the arrangements of the present invention can be adaptive to change continuously/periodically.
One prior art technique for accomplishing impedance matching of output pads for integrated circuits is described in U.S. Pat. No. 6,118,310 to Esch, Jr. and assigned to the same assignee of interest, entitled “Digitally Controlled Output Driver and Method for Impedance Matching”, herein incorporated by reference for all that it teaches. In the technique described therein, output driver impedance matching is accomplished by programmably enabling a combination of FETs arranged in parallel whose combined impedance closely matches the characteristic impedance of the transmission line.
Such prior art variable impedance output drivers typically use a pure thermometer code for the PVT impedance matching control in order to limit the change in output impedance when the PVT control code is updated. In particular, an impedance network having n parallel legs may implement an n-bit “thermometer” code T0::n-1. The state of each bit in the n-bit code T0::n-1 controls activation of respective legs in the impedance network. In a thermometer code, when a bit Ti of the code T0::n-1 is activated (set to “1”), all of the lower-order bits T1 to Ti-1 are also activated. Thus, in a pure thermometer code impedance matching circuit, a first impedance leg is activated and then each subsequent impedance leg is activated until the desired output impedance is achieved. Accordingly, at least one impedance leg is always activated to ensure that during the switching of impedance legs on or off, the impedance legs are never switched from all off to all on or vice versa, which would result in a spike in the output impedance. Table 1 illustrates a pure 11-bit thermometer code, wherein each bit 0::10 in the code word T represents an incremental admittance step of 10%—that is each impedance leg is weighted by a 10% incremental impedance amount.
TABLE 1Admit-Imped-tanceanceT10T9T8T7T6T5T4T3T2T1T0(Y = 1/Z)(Z)0000000000111000000000111 + .1.909000000001111 + .2.833000000011111 + .3.769000000111111 + .4.714000001111111 + .5.667000011111111 + .6.625000111111111 + .7.588001111111111 + .8.555011111111111 + .9.526
In the example thermometer code of TABLE 1, the controllable range of the output impedance is limited to between 1 and 0.526, and the sensitivity is 0.1 or 10% change in admittance for each step. As also illustrated by TABLE 1, a pure thermometer code requires one bit for each step. Accordingly, one of the drawbacks of a pure thermometer code is the large number of bits (and therefore control lines) required to allow a large range of output impedance. The number of control lines increases exponentially as the degree of required step sensitivity increases. For example, if it would be desirable to step the admittance only 1% in order to increase the sensitivity of each step, the PVT control circuit would require 101 control lines, or tenfold the number of lines required for adjusting it to the nearest 10%. Alternatively, if it were desired to increase the range of adjustable output impedance from 1 to 0.25, in the example of TABLE 1 with each step changing the admittance by 10%, an additional twenty bits (control lines) would be required.
Accordingly, although an increased sensitivity range for adjusting the PVT output impedance is desirable, the number of bits required to implement any significant range and/or sensitivity using a pure thermometer code is outweighed by the added design complexity and chip real estate required to implement it.
An alternative solution to use of a pure thermometer code is the use of a pure binary weighted code whereby each leg of the PVT control circuit is binary weighted to comprise a resistive device having an admittance corresponding to a combination of its binary weighted bit position. In other words, each impedance leg in the impedance network has an admittance of 2(bit position)Y, where Y is a predefined minimum admittance appropriate to the design. In other words, if bit B0 of a binary-coded calibration word B0::n-1 controls a FET with admittance Y, bit B1 of the calibration word B0::n-1 controls a FET with admittance 2*Y, bit B2 of the calibration word B0::n-1 controls a FET with admittance 4*Y, and so on. Thus, the impedance of each leg of the impedance network corresponds to the weighted position of the bit in the binary code that controls the leg. More particularly, if the calibration word B0::n-1 comprises 4 bits, the impedance leg controlled by bit B0 has a relative impedance weighting of 1. Similarly, the impedance leg controlled by bit B1 has a relative impedance weighting of 2, and the impedance leg controlled by bit B2 has a relative impedance weighting of 4, and the impedance leg controlled by bit B3 has a relative impedance weighting of 8. In effect, as the binary count of the calibration word B0::n-1 increments, more impedance is added in parallel in the impedance network, and the output impedance on the signal pad drops. TABLE 2 illustrates an example of a pure 4-bit binary weighted code.
TABLE 2AdmittanceImpedanceB3B2B1B0(Y = 1/Z)(Z)00000infinite00010.11000100.2500110.33.33301000.42.501010.5201100.61.66701110.71.42910000.81.2510010.91.1110101.0110111.1.90911001.2.83311011.3.76911101.4.71411111.5.667
As illustrated in TABLE 2, the benefit of using a binary weighted code is its ability to achieve a larger range of output impedance using fewer bits (or PVT control lines). However, in a pure binary weighted code, a step-wise increment does not ensure that all legs currently activated will remain activated at the next step. This can result in a jump in output impedance, which may cause partial reflection of a signal incoming from a transmission line coupled to the output pad. Further, if a transmission line is low because one of the drivers is active, the impedance transition may launch a wave onto the transmission line. This can result in an unacceptable noise glitch. For example, suppose the current binary weighted calibration code B that controls a 4-leg impedance network has a value of binary 0111 (corresponding to an admittance of 0.7) and the code B is to be incrementally stepped to binary 1000 (corresponding to an admittance value of 0.8). When the electrical connections of the impedance legs are switched from 0111 to 1000, it is possible that for a very short time the switches may be in a state such that all the switched impedance legs are simultaneously momentarily on (corresponding to a binary value of “1111”) or simultaneously momentarily off (corresponding to a binary value of “0000”). In this example and according to TABLE 2, the output impedance ZOUT could momentarily change from ZOUT=1.429 (corresponding to an admittance of 0.7) to ZOUT=0.667 (corresponding to an admittance of 1.5, or from ZOUT=1.429 (corresponding to an admittance of 0.7) to ZOUT=infinite (corresponding to an admittance of 1.5). As illustrated by this example, the more bits in the code that must be switched between one step value to the next increases the probability of an undesirable spike in the output impedance seen on the signal pad.
Hybrid PVT codes have been developed, for example as described in U.S. Pat. No. 6,326,802 to Newman et al., entitled “On-Die Adaptive Arrangements For Continuous Process, Voltage, And Temperature Compensation”, herein incorporated by reference for all that it teaches. In the technique described therein, PVT compensation is achieved using a hybrid binary/linear (thermometer) adaptive arrangement during initialization to initially adapt to an external resistor REXT, and thereafter locks the binary adaptive arrangement to the adapted impedance such that the binary adaptive arrangement cannot generate impedance/noise glitches after initialization. Once the binary adaptive arrangement has been used to initially adapt to REXT during initialization then the hybrid binary/linear adaptive arrangement utilizes a linear (thermometer) adaptive arrangement to continuously readapt to REXT to compensate for operational and environmental variations after initialization. However, while the hybrid binary/linear arrangement of U.S. Pat. No. 6,326,802 may be used to decrease the number of bits used for PVT compensation, the binary and linear arrangements are mutually exclusive during operation. Thus, during initialization, the output impedance is susceptible to impedance/noise glitches, and after initialization, the sensitivity range is limited by the number of bits lines.
Accordingly, a need exists for a PVT control encoding technique that allows for a higher output impedance range with fewer control lines, while preventing spikes in the output impedance on the signal pads.